1. Field of the Invention
The present invention generally relates to computer systems and, more particularly, to a method of controlling capacitors which are provided on a computer chip to enhance power supply, allowing testing of the computer system to determine the effects of the on-chip capacitors and allowing selective disabling of the capacitors as necessary.
2. Description of the Related Art
The basic structure of a conventional computer system includes a central processing unit (CPU) or processor which is connected to several peripheral devices, including input/output (I/O) devices (such as a display monitor and keyboard) for the user interface, a permanent memory device (such as a hard disk or floppy diskette) for storing the computer's operating system and user programs, and a temporary memory device (such as random-access memory or RAM) that is used by the processor to store instructions and data during program execution. The processor itself includes many different circuits, and these circuits are often fabricated on separate chips (silicon substrates), and then interconnected by various means. Recently, chip-fabrication techniques have allowed these circuits to be formed from a single die as shown in FIG. 1. Several exemplary circuits are depicted in that figure, including a fixed-point circuit 2, a floating-point circuit 4, a storage-control circuit 6, an instruction-control circuit 8, and a data-control circuit 10, all formed on a single computer chip 12. These circuits contain the various registers and logic units which carry out program instructions. Fabrication of the circuits on a single chip has several advantages, including quicker processing speeds and a smaller chip size.
One problem that has emerged in consolidating so many different circuits on a single chip relates to the power supply for the circuits. With so many circuits on a single chip, there can be degradations in processor performance due to, e.g., lag times associated with switching of latches in the processor registers and logic units, i.e., from low-voltage states to high-voltage states. One approach that has been implemented to address this problem is the further inclusion of many capacitors (tens of thousands) arranged in banks and distributed across (i.e., formed on) the chip, such as the capacitor banks 14 shown in FIG. 1 which are respectively connected to the various circuits and to a power supply 16. Such an approach allows the capacitors to instantaneously supply power to the circuits in an improved manner, relieving some of the performance degradation problems.
The provision of on-chip capacitors raises further concerns, however, particularly capacitor reliability and performance issues. There are concerns regarding how the capacitors function during processor operation and what their impact might be on the chip's functionality. Presently, there is no way to analyze this impact under different operating conditions and applications, such as burn-in and system environment conditions and functional and self-test applications. There is also no way to disable the capacitors in cases of unreliability and adverse electrical impacts that may have been introduced by the provision of the capacitors. It would, therefore, be desirable to devise a method of testing the reliability of on-chip capacitors and of determining the impact of these capacitors on processor performance. It would be further advantageous if the method would allow selective testing of a particular bank or banks of the capacitors, and if the method were compatible with a means for disabling the capacitors in those situations where the capacitors were either unreliable or created an excessively adverse impact on processor performance. Such disabling of the capacitors would be particularly useful if the disabling could be achieved without having to initialize the chip in certain states, such as after a power-on reset condition.